This position is for a Lead FPGA UVM (Universal Verification Methodology) Verification Engineer
• BS Degree in electrical/computer engineering and 9+ years of professional relevant experience, OR, a MS in electrical/computer engineering and 7+ years of professional relevant experience.
• 5+ years of experience verifying ASICs / FPGAs.
• 3+ years of experience with verification methodology like OVM / UVM.
Preferred Additional Skills:
• 3+ years of experience in ASIC / FPGA verification using C/C++ and/or System Verilog.
• 3+ years of experience with building and setting up scalable simulation/verification environments.
• Experience with and understanding of Altera and/or Xilinx FPGA architectures.
• Experience with Vivado and/or Quartus tool suite.
• Proficiency with hardware verification languages: System Verilog, System Verilog Assertions
• Proficiency with Object Oriented Programming Concepts: Inheritance, Polymorphism, etc.
• Proficient in scripting languages: bash/csh, Perl, Python, etc.
• Revision Control Systems: svn, git
• Proficient in Linux Environments
• Constrained Random Verification Experience highly desired.
• Experience with packet-based protocols (PCI Express etc.), Network-centric designs (Ethernet, IP, FC).
• Experience with high speed memory interfaces (DDRx)
• Familiarity with test scoping for complex designs, code coverage, functional coverage, assertions.