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Physical Design Engineer

Job Description

Job Description

  • Develop and own physical design implementation of multi-hierarchy low-power designs including physical-aware logic synthesis, design for testability, constraints, static timing analysis, formal verification, Gate level functional & timing ECO in advanced technology nodes
  • Develop & document STA & Synthesis strategies. Interact with methodology teams to address challenges related to new technology nodes.
  • Familiar with constraint checking tools and techniques to deliver quality constraints for both pre and post CTS views.
  • Resolve design and flow issues related to physical design, identify potential solutions, and drive execution
  • Proficiency in advanced synthesis & STA techniques to achieve aggressive low power, area, and timing goals. Must be able to drive solutions for complex timing closure scenarios.
  • Ability to optimize designs for best in class in low power and high performance with logically equivalent RTL transforms
  • Experience with multi-clock and multi-power domain designs.
  • Proficiency with ECO for functional and DFT timing closure
  • Deliver physical design of an end-to-end IP or integration of ASIC/SoC design.

Job Requirements

Minimum Qualifications:

  • Bachelor's degree in Electrical Engineering or Computer Science
  • 4-10 years’ experience
  • RTL2Gate experience on advanced technology nodes (7nm and below)

Job Snapshot

Location US-CA-San Francisco
Employment Type Contractor
Pay Type Year
Pay Rate N/A
Store Type Engineering & Aerospace
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Company Overview

ACS Solutions

ACS Group provides services to Fortune 1000 companies across various industry verticals. With a proven track record of managing project demands while improving the efficiency, productivity and profitability of new and existing projects through process improvement, ACS Group is consistently recognized for identifying and implementing strategic solutions that create and preserve long-term business value. Learn More

Contact Information

US-CA-San Francisco
Naval Sisodia
Snapshot
ACS Solutions
Company:
US-CA-San Francisco
Location:
Contractor
Employment Type:
Year
Pay Type:
N/A
Pay Rate:
Engineering & Aerospace
Store Type:

Job Description

Job Description

  • Develop and own physical design implementation of multi-hierarchy low-power designs including physical-aware logic synthesis, design for testability, constraints, static timing analysis, formal verification, Gate level functional & timing ECO in advanced technology nodes
  • Develop & document STA & Synthesis strategies. Interact with methodology teams to address challenges related to new technology nodes.
  • Familiar with constraint checking tools and techniques to deliver quality constraints for both pre and post CTS views.
  • Resolve design and flow issues related to physical design, identify potential solutions, and drive execution
  • Proficiency in advanced synthesis & STA techniques to achieve aggressive low power, area, and timing goals. Must be able to drive solutions for complex timing closure scenarios.
  • Ability to optimize designs for best in class in low power and high performance with logically equivalent RTL transforms
  • Experience with multi-clock and multi-power domain designs.
  • Proficiency with ECO for functional and DFT timing closure
  • Deliver physical design of an end-to-end IP or integration of ASIC/SoC design.

Job Requirements

Minimum Qualifications:

  • Bachelor's degree in Electrical Engineering or Computer Science
  • 4-10 years’ experience
  • RTL2Gate experience on advanced technology nodes (7nm and below)
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Physical Design Engineer Apply now