Location Palm Bay, FL 32905
Duration 06 Months
Job Description:Utilize high-level architectural documentation along with algorithm descriptions to create self-checking and reusable test benches from scratch. Develop reusable agents, top level testbench modules and environments Define and implement functional coverage model based upon DUT requirements and close code coverage. Utilize UVM to create drivers, monitors, predictors, and scoreboards based on DUT requirements. Thorough understanding of FPGA design process including requirements generation, preliminary design, peer reviews, detailed design, test plan generation, and integration and test. Work independently to develop test bench solutions. Preferred Additional Skills: 3+ years of experience in ASIC / FPGA verification using C/C++ and/or System Verilog. 3+ years of experience with building and setting up scalable simulation/verification environments. Experience with and understanding of Altera and/or Xilinx FPGA architectures. Experience with Vivado and/or Quartus tool suite. Ability to obtain a Secret security clearance. Proficiency with hardware verification languages: System Verilog, System Verilog Assertions Proficiency with Object Oriented Programming Concepts: Inheritance, Polymorphism, etc. Proficient in scripting languages: bash/csh, Perl, Python, etc. Revision Control Systems: svn, git Proficient in Linux Environments Constrained Random Verification Experience highly desired. Experience with packet-based protocols (PCI Express etc.), Network-centric designs (Ethernet, IP, FC). Experience with high speed memory interfaces (DDRx) Familiarity with test scoping for complex designs, code coverage, functional coverage, assertions. Ability to focus on finding design issues, corner cases and out of box ideas to make designs more robust.
Ability to work in a team environment and negotiate solutions with Hardware / Software Engineering and Systems Engineering is desired.